[PATCH] D124734: [AMDGPU] Fix scalar_to_vector for v8i16/v8f16

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2710
+  (v8i16 (scalar_to_vector i16:$src0)),
+  (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
+>;
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I don’t think these should be legal. We don’t naturally have 8 X 16 operations. A lowering that splits the vector would avoid introducing the wider registers and may combine better 


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  https://reviews.llvm.org/D124734/new/

https://reviews.llvm.org/D124734