[PATCH] D124723: [MIPS} Address ISel failures for 64 bit fpus in microMIPS

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
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Add the instructions and patterns for loads and stores in microMIPSr3
when a 64 bit FPU is present. Previously, this would lead to an
instruction selection failure.

This resolves PR/49200.

Thanks to jdeguire for reporting the issue!


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124723

Files:
  llvm/lib/Target/Mips/MicroMipsInstrFPU.td
  llvm/lib/Target/Mips/MipsScheduleGeneric.td
  llvm/test/CodeGen/Mips/llvm-ir/load.ll
  llvm/test/CodeGen/Mips/llvm-ir/store.ll
  llvm/test/CodeGen/Mips/pr49200.ll

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