[PATCH] D124526: [SimpleLoopUnswitch] Collect either logical ANDs/ORs but not both.

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


================
Comment at: llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp:124
+  while (match(Cond, m_Select(m_Value(CondNext), m_One(), m_Zero())))
+    Cond = CondNext;
+
----------------
Might make more sense to do the stripping as a separate step `Cond = stripTrivialSelect(Cond)`, just without the bit that actually updates the condition in the branch instruction?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124526/new/

https://reviews.llvm.org/D124526