[llvm] f10a8f6 - [LegalizeDAG] Fix TypeSize conversion error when expanding SIGN_EXTEND_INREG

[Paul Walker via llvm-commits]

Author: Paul Walker
Date: 2022-04-30T19:21:48+01:00
New Revision: f10a8f675285177d4d720ace0dcdb6a8e714b888

URL: https://github.com/llvm/llvm-project/commit/f10a8f675285177d4d720ace0dcdb6a8e714b888
DIFF: https://github.com/llvm/llvm-project/commit/f10a8f675285177d4d720ace0dcdb6a8e714b888.diff

LOG: [LegalizeDAG] Fix TypeSize conversion error when expanding SIGN_EXTEND_INREG

SIGN_EXTEND_INREG expansion can trigger a TypeSize error because
"VT.getSizeInBits() == 1" is used to detect for a boolean without
first verifying VT is a scalar.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/test/CodeGen/AArch64/sve-sext-zext.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 64f2c4c571d40..3b9f47702cafb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2918,7 +2918,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
     // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
 
     // TODO: Do this for vectors too?
-    if (ExtraVT.getSizeInBits() == 1) {
+    if (ExtraVT.isScalarInteger() && ExtraVT.getSizeInBits() == 1) {
       SDValue One = DAG.getConstant(1, dl, VT);
       SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
       SDValue Zero = DAG.getConstant(0, dl, VT);

diff  --git a/llvm/test/CodeGen/AArch64/sve-sext-zext.ll b/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
index dc77dc838ae9f..6514ab03ae515 100644
--- a/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
+++ b/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
@@ -326,3 +326,24 @@ define <vscale x 16 x i64> @zext_b_to_d(<vscale x 16 x i8> %a) {
   %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i64>
   ret <vscale x 16 x i64> %ext
 }
+
+; Extending non power-of-two types
+
+define <vscale x 2 x i64> @sext_i18_i64(<vscale x 2 x i18> %a) {
+; CHECK-LABEL: sext_i18_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.d, z0.d, #46
+; CHECK-NEXT:    asr z0.d, z0.d, #46
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i18> %a to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @zext_i18_i64(<vscale x 2 x i18> %a) {
+; CHECK-LABEL: zext_i18_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and z0.d, z0.d, #0x3ffff
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i18> %a to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %r
+}