[PATCH] D124716: [MIPS] Remove an incorrect microMIPS instruction alias

[Simon Dardis via Phabricator via llvm-commits]

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The microMIPS instruction set is compatible with the MIPS instruction
set at the assembly level but not in terms of encodings. `nop` in
microMIPS is a special case as it has the same encoding as `nop` for
MIPS.

Fix this error by reducing the usage of NOP in the MIPS backend such
that only that ISA correct variants are produced.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124716

Files:
  llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
  llvm/lib/Target/Mips/MicroMipsInstrInfo.td
  llvm/lib/Target/Mips/MipsBranchExpansion.cpp
  llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
  llvm/lib/Target/Mips/MipsInstrInfo.cpp
  llvm/lib/Target/Mips/MipsInstrInfo.h
  llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
  llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
  llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir

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