[llvm] e098281 - [RISCV] Don't getDebugLoc for the end node of MBB iterator

[via llvm-commits]

Author: luxufan
Date: 2022-04-30T16:00:20+08:00
New Revision: e098281c278cd1d840d6ee28d63a7d9671abbe4b

URL: https://github.com/llvm/llvm-project/commit/e098281c278cd1d840d6ee28d63a7d9671abbe4b
DIFF: https://github.com/llvm/llvm-project/commit/e098281c278cd1d840d6ee28d63a7d9671abbe4b.diff

LOG: [RISCV] Don't getDebugLoc for the end node of MBB iterator

Because of shrink wrapping, the block to insert epilog may don't have
instructions (Only debug instructions). And the position to insert may
point to MBB.end() that don't have a DebugLoc. This patch fix this
problem.

The test program was copied from the issue:https://github.com/llvm/llvm-project/issues/53662

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D123679

Added: 
    llvm/test/CodeGen/RISCV/pr53662.mir

Modified: 
    llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8f250eeb7248a..e7673ea95502b 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -561,15 +561,11 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
   MachineBasicBlock::iterator MBBI = MBB.end();
   DebugLoc DL;
   if (!MBB.empty()) {
+    MBBI = MBB.getLastNonDebugInstr();
+    if (MBBI != MBB.end())
+      DL = MBBI->getDebugLoc();
+
     MBBI = MBB.getFirstTerminator();
-    if (MBBI == MBB.end())
-      MBBI = MBB.getLastNonDebugInstr();
-    DL = MBBI->getDebugLoc();
-
-    // If this is not a terminator, the actual insert location should be after the
-    // last instruction.
-    if (!MBBI->isTerminator())
-      MBBI = std::next(MBBI);
 
     // If callee-saved registers are saved via libcall, place stack adjustment
     // before this call.

diff  --git a/llvm/test/CodeGen/RISCV/pr53662.mir b/llvm/test/CodeGen/RISCV/pr53662.mir
new file mode 100644
index 0000000000000..ce5e5e811f2c6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr53662.mir
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -o - %s | FileCheck %s
+--- |
+  define void @b() {
+  entry:
+    unreachable
+  }
+
+...
+---
+name:            b
+frameInfo:
+  savePoint:       '%bb.0'
+  restorePoint:    '%bb.1'
+body:             |
+  ; CHECK-LABEL: name: b
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   DBG_VALUE $noreg
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   PseudoRET implicit killed $x10
+  bb.0 :
+    PseudoBR %bb.1
+
+  bb.1:
+    DBG_VALUE $noreg
+
+  bb.2:
+    PseudoRET implicit killed $x10
+
+...