[PATCH] D124709: [InstCombine][NFC] Add baseline tests for folds of ((A&B)^C)|B

[Alexander Shaposhnikov via Phabricator via llvm-commits]

alexander-shaposhnikov created this revision.
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Baseline tests (preparations to address https://github.com/llvm/llvm-project/issues/55169 ).

Test plan: ninja check-llvm


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124709

Files:
  llvm/test/Transforms/InstCombine/and-xor-or.ll


Index: llvm/test/Transforms/InstCombine/and-xor-or.ll
===================================================================
--- llvm/test/Transforms/InstCombine/and-xor-or.ll
+++ llvm/test/Transforms/InstCombine/and-xor-or.ll
@@ -168,6 +168,36 @@
   ret i64 %3
 }
 
+; ((x & y) + z) | y -> (z | y)
+
+define i64 @and_xor_or1(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: @and_xor_or1(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = xor i64 [[TMP1]], [[Z:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = or i64 [[TMP2]], [[Y]]
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
+  %1 = and i64 %x, %y
+  %2 = xor i64 %1, %z
+  %3 = or i64 %2, %y
+  ret i64 %3
+}
+
+; y | ((x & y) + z) -> (z | y)
+
+define i64 @and_xor_or2(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: @and_xor_or2(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = xor i64 [[TMP1]], [[Z:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = or i64 [[TMP2]], [[Y]]
+; CHECK-NEXT:    ret i64 [[TMP3]]
+;
+  %1 = and i64 %x, %y
+  %2 = xor i64 %1, %z
+  %3 = or i64 %y, %2
+  ret i64 %3
+}
+
 ; PR37098 - https://bugs.llvm.org/show_bug.cgi?id=37098
 ; Reassociate bitwise logic to eliminate a shift.
 ; There are 4 commuted * 3 shift ops * 3 logic ops = 36 potential variations of this fold.


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