[PATCH] D124697: Distinguish between different forms of "address-taken" MachineBasicBlocks

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
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There are two different senses in which a block can be "address-taken". There can be a BlockAddress involved, which means we need to map the IR-level value to some specific block of machine code.  Or there can be constructs inside a function which involve using the address of a basic block to implement certain kinds of control flow.

Mixing these together causes a problem: if target-specific passes are marking random blocks "address-taken", if we have a BlockAddress, we can't actually tell which MachineBasicBlock corresponds to the BlockAddress.

So split this into two separate bits: one for BlockAddress, and one for the machine-specific bits.  And try to clarify when, exactly, it's appropriate to use the new setMBBLabelUsed().

Discovered while trying to sort out related stuff on D102817 <https://reviews.llvm.org/D102817>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124697

Files:
  llvm/include/llvm/CodeGen/MachineBasicBlock.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineBasicBlock.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86IndirectThunks.cpp
  llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
  llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
  llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
  llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
  llvm/test/CodeGen/ARM/ifcvt-size.mir
  llvm/test/CodeGen/Hexagon/bank-conflict.mir
  llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
  llvm/test/CodeGen/Hexagon/loop_correctness.ll
  llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
  llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
  llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
  llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
  llvm/test/CodeGen/MIR/X86/block-address-operands.mir
  llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
  llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
  llvm/test/CodeGen/X86/callbr-asm-kill.mir
  llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
  llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
  llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
  llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
  llvm/tools/llvm-reduce/ReducerWorkItem.cpp

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