[PATCH] D124696: [SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: efriedma, spatel, RKSimon, regehr.
Herald added subscribers: StephenFan, ecnelises, hiraditya.
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The result of sign_extend_inreg needs to have as many sign bits
as requested by the VT argument. The easiest way to guarantee this
is to fold it to 0.

Fixes https://github.com/llvm/llvm-project/issues/55178

Not sure if the SystemZ test is still testing the same thing it
was before.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124696

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/pr55178.ll
  llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll


Index: llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
+++ llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
@@ -14,17 +14,15 @@
 define void @main() {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    larl %r2, g_151
 ; CHECK-NEXT:    lhi %r0, 1
-; CHECK-NEXT:    larl %r1, g_151
-; CHECK-NEXT:    lghi %r3, 0
-; CHECK-NEXT:    chi %r0, 0
-; CHECK-NEXT:    locghile %r3, 1
-; CHECK-NEXT:    o %r0, 0(%r1)
-; CHECK-NEXT:    dsgfr %r2, %r0
-; CHECK-NEXT:    larl %r1, g_222
-; CHECK-NEXT:    lghi %r5, 0
-; CHECK-NEXT:    stgrl %r2, g_39
-; CHECK-NEXT:    stc %r5, 19(%r1)
+; CHECK-NEXT:    o %r0, 0(%r2)
+; CHECK-NEXT:    lghi %r1, 1
+; CHECK-NEXT:    larl %r2, g_222
+; CHECK-NEXT:    dsgfr %r0, %r0
+; CHECK-NEXT:    lghi %r1, 0
+; CHECK-NEXT:    stgrl %r0, g_39
+; CHECK-NEXT:    stc %r1, 19(%r2)
 ; CHECK-NEXT:    br %r14
   %tmp = load i32, i32* @g_151, align 4
   %tmp3 = or i32 %tmp, 1
Index: llvm/test/CodeGen/AArch64/pr55178.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/pr55178.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
+
+; This used to generate incorrect code because we sign extended
+; the undef to undef instead of to 0.
+
+define i1 @test14(i8 %X) {
+; CHECK-LABEL: test14:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-113
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    lsl w8, w8, w0
+; CHECK-NEXT:    sxtb w8, w8
+; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    cset w0, gt
+; CHECK-NEXT:    ret
+  %1 = shl i8 -113, %X
+  %cmp = icmp slt i8 undef, %1
+  ret i1 %cmp
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6197,9 +6197,9 @@
       std::swap(N1, N2);
     } else {
       switch (Opcode) {
-      case ISD::SIGN_EXTEND_INREG:
       case ISD::SUB:
         return getUNDEF(VT);     // fold op(undef, arg2) -> undef
+      case ISD::SIGN_EXTEND_INREG:
       case ISD::UDIV:
       case ISD::SDIV:
       case ISD::UREM:


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