[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1263
+      if (MI.getOpcode() == AMDGPU::V_WRITELANE_B32)
+        MFI->addToLaneVGPRs(MF, MI.getOperand(0).getReg());
+    }
----------------
arsenm wrote:
> I don't think this is the right place to determine these registers. It's adding an extra loop over the function, and adding statefulness to determineCalleeSaves. Theoretically we should be able to call it multiple times 
Any recommendation?
This should be done before identifying the CSR registers and they should be skipped from the default CSR spill insertion routines.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192