[llvm] 2d7f0b1 - [X86] Fold ANDNP(undef,x)/ANDNP(x,undef) -> 0

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-04-29T10:20:48+01:00
New Revision: 2d7f0b1c2216108ed46fa25324a727614f58ee12

URL: https://github.com/llvm/llvm-project/commit/2d7f0b1c2216108ed46fa25324a727614f58ee12
DIFF: https://github.com/llvm/llvm-project/commit/2d7f0b1c2216108ed46fa25324a727614f58ee12.diff

LOG: [X86] Fold ANDNP(undef,x)/ANDNP(x,undef) -> 0

Matches the fold in DAGCombiner::visitANDLike.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/pr55158.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0bc783fb982b..e7299c7088b2 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50665,6 +50665,11 @@ static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG,
   SDValue N1 = N->getOperand(1);
   MVT VT = N->getSimpleValueType(0);
 
+  // ANDNP(undef, x) -> 0
+  // ANDNP(x, undef) -> 0
+  if (N0.isUndef() || N1.isUndef())
+    return DAG.getConstant(0, SDLoc(N), VT);
+
   // ANDNP(0, x) -> x
   if (ISD::isBuildVectorAllZeros(N0.getNode()))
     return N1;

diff  --git a/llvm/test/CodeGen/X86/pr55158.ll b/llvm/test/CodeGen/X86/pr55158.ll
index b278812228c2..bac6e4893fc8 100644
--- a/llvm/test/CodeGen/X86/pr55158.ll
+++ b/llvm/test/CodeGen/X86/pr55158.ll
@@ -1,33 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-linux -opaque-pointers -mcpu=ivybridge -mattr=+avx2 | FileCheck %s --check-prefixes=IVB
-; RUN: llc < %s -mtriple=x86_64-linux -opaque-pointers -mcpu=haswell | FileCheck %s --check-prefixes=HSW
+; RUN: llc < %s -mtriple=x86_64-linux -opaque-pointers -mcpu=ivybridge -mattr=+avx2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux -opaque-pointers -mcpu=haswell | FileCheck %s
 
 define <2 x i64> @PR55158(ptr %0) {
-; IVB-LABEL: PR55158:
-; IVB:       # %bb.0:
-; IVB-NEXT:    vmovdqa 64(%rdi), %xmm0
-; IVB-NEXT:    vmovdqa 128(%rdi), %xmm1
-; IVB-NEXT:    vpmovsxbd (%rdi), %xmm2
-; IVB-NEXT:    vpcmpgtd %xmm2, %xmm1, %xmm1
-; IVB-NEXT:    vphsubw %xmm0, %xmm0, %xmm0
-; IVB-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
-; IVB-NEXT:    vpxor %xmm2, %xmm2, %xmm2
-; IVB-NEXT:    vpsrlvq %xmm1, %xmm2, %xmm1
-; IVB-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
-; IVB-NEXT:    retq
-;
-; HSW-LABEL: PR55158:
-; HSW:       # %bb.0:
-; HSW-NEXT:    vmovdqa 64(%rdi), %xmm0
-; HSW-NEXT:    vmovdqa 128(%rdi), %xmm1
-; HSW-NEXT:    vpmovsxbd (%rdi), %xmm2
-; HSW-NEXT:    vpcmpgtd %xmm2, %xmm1, %xmm1
-; HSW-NEXT:    vphsubw %xmm0, %xmm0, %xmm0
-; HSW-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
-; HSW-NEXT:    vpandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
-; HSW-NEXT:    vpsrlvq %xmm1, %xmm2, %xmm1
-; HSW-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
-; HSW-NEXT:    retq
+; CHECK-LABEL: PR55158:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmovdqa 64(%rdi), %xmm0
+; CHECK-NEXT:    vmovdqa 128(%rdi), %xmm1
+; CHECK-NEXT:    vpmovsxbd (%rdi), %xmm2
+; CHECK-NEXT:    vpcmpgtd %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vphsubw %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
+; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpsrlvq %xmm1, %xmm2, %xmm1
+; CHECK-NEXT:    vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
+; CHECK-NEXT:    retq
   %2 = load <16 x i8>, ptr %0, align 16
   %3 = getelementptr inbounds i32, ptr %0, i64 16
   %4 = load <8 x i16>, ptr %3, align 16