[llvm] c96cc50 - [SystemZ] Custom lowering of llvm.is_fpclass
Serge Pavlov via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 29 00:29:14 PDT 2022
Author: Serge Pavlov
Date: 2022-04-29T13:27:36+07:00
New Revision: c96cc500f0b31bd881d38b2b16ee9c1fef0307e4
URL: https://github.com/llvm/llvm-project/commit/c96cc500f0b31bd881d38b2b16ee9c1fef0307e4
DIFF: https://github.com/llvm/llvm-project/commit/c96cc500f0b31bd881d38b2b16ee9c1fef0307e4.diff
LOG: [SystemZ] Custom lowering of llvm.is_fpclass
Differential Revision: https://reviews.llvm.org/D114695
Added:
llvm/test/CodeGen/SystemZ/is_fpclass.ll
Modified:
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 1fbc1e6881189..db629469d0495 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -471,6 +471,9 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FREM, VT, Expand);
setOperationAction(ISD::FPOW, VT, Expand);
+ // Special treatment.
+ setOperationAction(ISD::IS_FPCLASS, VT, Custom);
+
// Handle constrained floating-point operations.
setOperationAction(ISD::STRICT_FADD, VT, Legal);
setOperationAction(ISD::STRICT_FSUB, VT, Legal);
@@ -5615,6 +5618,41 @@ SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
return Op;
}
+SDValue SystemZTargetLowering::lowerIS_FPCLASS(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ MVT ResultVT = Op.getSimpleValueType();
+ SDValue Arg = Op.getOperand(0);
+ auto CNode = cast<ConstantSDNode>(Op.getOperand(1));
+ unsigned Check = CNode->getZExtValue();
+
+ unsigned TDCMask = 0;
+ if (Check & fcSNan)
+ TDCMask |= SystemZ::TDCMASK_SNAN_PLUS | SystemZ::TDCMASK_SNAN_MINUS;
+ if (Check & fcQNan)
+ TDCMask |= SystemZ::TDCMASK_QNAN_PLUS | SystemZ::TDCMASK_QNAN_MINUS;
+ if (Check & fcPosInf)
+ TDCMask |= SystemZ::TDCMASK_INFINITY_PLUS;
+ if (Check & fcNegInf)
+ TDCMask |= SystemZ::TDCMASK_INFINITY_MINUS;
+ if (Check & fcPosNormal)
+ TDCMask |= SystemZ::TDCMASK_NORMAL_PLUS;
+ if (Check & fcNegNormal)
+ TDCMask |= SystemZ::TDCMASK_NORMAL_MINUS;
+ if (Check & fcPosSubnormal)
+ TDCMask |= SystemZ::TDCMASK_SUBNORMAL_PLUS;
+ if (Check & fcNegSubnormal)
+ TDCMask |= SystemZ::TDCMASK_SUBNORMAL_MINUS;
+ if (Check & fcPosZero)
+ TDCMask |= SystemZ::TDCMASK_ZERO_PLUS;
+ if (Check & fcNegZero)
+ TDCMask |= SystemZ::TDCMASK_ZERO_MINUS;
+ SDValue TDCMaskV = DAG.getConstant(TDCMask, DL, MVT::i32);
+
+ SDValue Intr = DAG.getNode(SystemZISD::TDC, DL, ResultVT, Arg, TDCMaskV);
+ return getCCResult(DAG, Intr);
+}
+
SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
@@ -5732,6 +5770,8 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
case ISD::SRA:
return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
+ case ISD::IS_FPCLASS:
+ return lowerIS_FPCLASS(Op, DAG);
default:
llvm_unreachable("Unexpected node to lower");
}
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 0f104e56b9587..aeb0419c8bb26 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -680,6 +680,7 @@ class SystemZTargetLowering : public TargetLowering {
SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
+ SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
bool canTreatAsByteVector(EVT VT) const;
SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
diff --git a/llvm/test/CodeGen/SystemZ/is_fpclass.ll b/llvm/test/CodeGen/SystemZ/is_fpclass.ll
new file mode 100644
index 0000000000000..7a02730047d20
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/is_fpclass.ll
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; Test intrinsic 'is_fpclass'.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare i1 @llvm.is.fpclass.f32(float, i32)
+declare i1 @llvm.is.fpclass.f64(double, i32)
+declare i1 @llvm.is.fpclass.f128(fp128, i32)
+
+
+define i1 @isnan_f(float %x) {
+; CHECK-LABEL: isnan_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 15
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
+ ret i1 %1
+}
+
+define i1 @isnan_d(double %x) {
+; CHECK-LABEL: isnan_d:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tcdb %f0, 15
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
+ ret i1 %1
+}
+
+define i1 @isnan_x(fp128 %x) {
+; CHECK-LABEL: isnan_x:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ld %f0, 0(%r2)
+; CHECK-NEXT: ld %f2, 8(%r2)
+; CHECK-NEXT: tcxb %f0, 15
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3) ; nan
+ ret i1 %1
+}
+
+define i1 @isqnan_f(float %x) {
+; CHECK-LABEL: isqnan_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 12
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; qnan
+ ret i1 %1
+}
+
+define i1 @issnan_f(float %x) {
+; CHECK-LABEL: issnan_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 3
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; snan
+ ret i1 %1
+}
+
+define i1 @isinf_f(float %x) {
+; CHECK-LABEL: isinf_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 48
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
+ ret i1 %1
+}
+
+define i1 @isposinf_f(float %x) {
+; CHECK-LABEL: isposinf_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 32
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"
+ ret i1 %1
+}
+
+define i1 @isneginf_f(float %x) {
+; CHECK-LABEL: isneginf_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 16
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"
+ ret i1 %1
+}
+
+define i1 @isfinite_f(float %x) {
+; CHECK-LABEL: isfinite_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 4032
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
+ ret i1 %1
+}
+
+define i1 @isposfinite_f(float %x) {
+; CHECK-LABEL: isposfinite_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 2688
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"
+ ret i1 %1
+}
+
+define i1 @isnegfinite_f(float %x) {
+; CHECK-LABEL: isnegfinite_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 1344
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite"
+ ret i1 %1
+}
+
+define i1 @isnotfinite_f(float %x) {
+; CHECK-LABEL: isnotfinite_f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tceb %f0, 63
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"
+ ret i1 %1
+}
+
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