[llvm] 181dcbd - [RISCV] Add riscv32 RUN lines to bittest.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 28 13:02:44 PDT 2022
Author: Craig Topper
Date: 2022-04-28T13:02:13-07:00
New Revision: 181dcbd36dd51e376018a13ecee560ba2b41d37a
URL: https://github.com/llvm/llvm-project/commit/181dcbd36dd51e376018a13ecee560ba2b41d37a
DIFF: https://github.com/llvm/llvm-project/commit/181dcbd36dd51e376018a13ecee560ba2b41d37a.diff
LOG: [RISCV] Add riscv32 RUN lines to bittest.ll. NFC
Add extra check-prefixes to merge common results.
Added:
Modified:
llvm/test/CodeGen/RISCV/bittest.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/bittest.ll b/llvm/test/CodeGen/RISCV/bittest.ll
index 45676348ebe0..b2a1ba0508ea 100644
--- a/llvm/test/CodeGen/RISCV/bittest.ll
+++ b/llvm/test/CodeGen/RISCV/bittest.ll
@@ -1,21 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV32,RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64I
+; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV64,RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64ZBS
+; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: bittest_7_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 128
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: bittest_7_i32:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: andi a0, a0, 128
-; RV64ZBS-NEXT: seqz a0, a0
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: bittest_7_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi a0, a0, 128
+; CHECK-NEXT: seqz a0, a0
+; CHECK-NEXT: ret
%shr = lshr i32 %a, 7
%not = xor i32 %shr, -1
%and = and i32 %not, 1
@@ -23,17 +21,11 @@ define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
}
define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: bittest_10_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1024
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: bittest_10_i32:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: andi a0, a0, 1024
-; RV64ZBS-NEXT: seqz a0, a0
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: bittest_10_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi a0, a0, 1024
+; CHECK-NEXT: seqz a0, a0
+; CHECK-NEXT: ret
%shr = lshr i32 %a, 10
%not = xor i32 %shr, -1
%and = and i32 %not, 1
@@ -41,18 +33,18 @@ define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
}
define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: bittest_11_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srli a0, a0, 11
-; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: ret
+; NOZBS-LABEL: bittest_11_i32:
+; NOZBS: # %bb.0:
+; NOZBS-NEXT: srli a0, a0, 11
+; NOZBS-NEXT: not a0, a0
+; NOZBS-NEXT: andi a0, a0, 1
+; NOZBS-NEXT: ret
;
-; RV64ZBS-LABEL: bittest_11_i32:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bexti a0, a0, 11
-; RV64ZBS-NEXT: xori a0, a0, 1
-; RV64ZBS-NEXT: ret
+; ZBS-LABEL: bittest_11_i32:
+; ZBS: # %bb.0:
+; ZBS-NEXT: bexti a0, a0, 11
+; ZBS-NEXT: xori a0, a0, 1
+; ZBS-NEXT: ret
%shr = lshr i32 %a, 11
%not = xor i32 %shr, -1
%and = and i32 %not, 1
@@ -60,17 +52,17 @@ define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
}
define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: bittest_31_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srliw a0, a0, 31
-; RV64I-NEXT: ret
+; RV32-LABEL: bittest_31_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: not a0, a0
+; RV32-NEXT: srli a0, a0, 31
+; RV32-NEXT: ret
;
-; RV64ZBS-LABEL: bittest_31_i32:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: not a0, a0
-; RV64ZBS-NEXT: srliw a0, a0, 31
-; RV64ZBS-NEXT: ret
+; RV64-LABEL: bittest_31_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: not a0, a0
+; RV64-NEXT: srliw a0, a0, 31
+; RV64-NEXT: ret
%shr = lshr i32 %a, 31
%not = xor i32 %shr, -1
%and = and i32 %not, 1
@@ -78,17 +70,18 @@ define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
}
define i64 @bittest_7_i64(i64 %a) nounwind {
-; RV64I-LABEL: bittest_7_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 128
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: ret
+; RV32-LABEL: bittest_7_i64:
+; RV32: # %bb.0:
+; RV32-NEXT: andi a0, a0, 128
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: ret
;
-; RV64ZBS-LABEL: bittest_7_i64:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: andi a0, a0, 128
-; RV64ZBS-NEXT: seqz a0, a0
-; RV64ZBS-NEXT: ret
+; RV64-LABEL: bittest_7_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 128
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: ret
%shr = lshr i64 %a, 7
%not = xor i64 %shr, -1
%and = and i64 %not, 1
@@ -96,17 +89,18 @@ define i64 @bittest_7_i64(i64 %a) nounwind {
}
define i64 @bittest_10_i64(i64 %a) nounwind {
-; RV64I-LABEL: bittest_10_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1024
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: ret
+; RV32-LABEL: bittest_10_i64:
+; RV32: # %bb.0:
+; RV32-NEXT: andi a0, a0, 1024
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: ret
;
-; RV64ZBS-LABEL: bittest_10_i64:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: andi a0, a0, 1024
-; RV64ZBS-NEXT: seqz a0, a0
-; RV64ZBS-NEXT: ret
+; RV64-LABEL: bittest_10_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1024
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: ret
%shr = lshr i64 %a, 10
%not = xor i64 %shr, -1
%and = and i64 %not, 1
@@ -114,6 +108,14 @@ define i64 @bittest_10_i64(i64 %a) nounwind {
}
define i64 @bittest_11_i64(i64 %a) nounwind {
+; RV32I-LABEL: bittest_11_i64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a0, a0, 11
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: andi a0, a0, 1
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: ret
+;
; RV64I-LABEL: bittest_11_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 11
@@ -121,6 +123,13 @@ define i64 @bittest_11_i64(i64 %a) nounwind {
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
+; RV32ZBS-LABEL: bittest_11_i64:
+; RV32ZBS: # %bb.0:
+; RV32ZBS-NEXT: bexti a0, a0, 11
+; RV32ZBS-NEXT: xori a0, a0, 1
+; RV32ZBS-NEXT: li a1, 0
+; RV32ZBS-NEXT: ret
+;
; RV64ZBS-LABEL: bittest_11_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 11
@@ -133,6 +142,13 @@ define i64 @bittest_11_i64(i64 %a) nounwind {
}
define i64 @bittest_31_i64(i64 %a) nounwind {
+; RV32-LABEL: bittest_31_i64:
+; RV32: # %bb.0:
+; RV32-NEXT: not a0, a0
+; RV32-NEXT: srli a0, a0, 31
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: ret
+;
; RV64I-LABEL: bittest_31_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 31
@@ -152,6 +168,13 @@ define i64 @bittest_31_i64(i64 %a) nounwind {
}
define i64 @bittest_32_i64(i64 %a) nounwind {
+; RV32-LABEL: bittest_32_i64:
+; RV32: # %bb.0:
+; RV32-NEXT: not a0, a1
+; RV32-NEXT: andi a0, a0, 1
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: ret
+;
; RV64I-LABEL: bittest_32_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 32
@@ -171,17 +194,18 @@ define i64 @bittest_32_i64(i64 %a) nounwind {
}
define i64 @bittest_63_i64(i64 %a) nounwind {
-; RV64I-LABEL: bittest_63_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a0, a0, 63
-; RV64I-NEXT: ret
+; RV32-LABEL: bittest_63_i64:
+; RV32: # %bb.0:
+; RV32-NEXT: not a0, a1
+; RV32-NEXT: srli a0, a0, 31
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: ret
;
-; RV64ZBS-LABEL: bittest_63_i64:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: not a0, a0
-; RV64ZBS-NEXT: srli a0, a0, 63
-; RV64ZBS-NEXT: ret
+; RV64-LABEL: bittest_63_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: not a0, a0
+; RV64-NEXT: srli a0, a0, 63
+; RV64-NEXT: ret
%shr = lshr i64 %a, 63
%not = xor i64 %shr, -1
%and = and i64 %not, 1
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