[llvm] 05b0a49 - [AArch64] Add a fp128 shuffle test. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2022-04-28T14:28:45+01:00
New Revision: 05b0a498329c4b5db367120e5c9358bb74346131

URL: https://github.com/llvm/llvm-project/commit/05b0a498329c4b5db367120e5c9358bb74346131
DIFF: https://github.com/llvm/llvm-project/commit/05b0a498329c4b5db367120e5c9358bb74346131.diff

LOG: [AArch64] Add a fp128 shuffle test. NFC

These legalize to scalar types, so it's useful to have a test case that
covers them.

Added: 
    

Modified: 
    llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
index 3a3c7802dbf01..3d808c7ed444a 100644
--- a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
@@ -15,6 +15,7 @@ define void @shuffle() {
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v15 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 0>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v17 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 0>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v18 = shufflevector <2 x fp128> undef, <2 x fp128> undef, <2 x i32> <i32 1, i32 0>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
   %v7 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> <i32 1, i32 0>
@@ -33,6 +34,8 @@ define void @shuffle() {
   %v16 = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> <i32 1, i32 0>
   %v17 = shufflevector <4 x float> undef, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 0>
 
+  %v18 = shufflevector <2 x fp128> undef, <2 x fp128> undef, <2 x i32> <i32 1, i32 0>
+
   ret void
 }