[PATCH] D124374: [RISCV][TargetLowering] Special case overflow expansion for (uaddo X, C).

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/xaluo.ll:4227
+; RV64-NEXT:    addi a0, a0, 2
+; RV64-NEXT:    li a1, 2
+; RV64-NEXT:    bgeu a0, a1, .LBB69_2
----------------
craig.topper wrote:
> This is materializing a constant in a register which we didn't need to do before. Looking at the generated code before this patch, there was a move instruction, but I think that was because of register allocation constraints from above and below.
> 
> If we change the test to this, then this patch increases instructions.
> 
> ```
> define i64 @uaddo.i64.constant_setcc_on_overflow_flag(i64* %p) {
> entry:
>   %v1 = load i64, i64* %p
>   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
>   %val = extractvalue {i64, i1} %t, 0
>   %obit = extractvalue {i64, i1} %t, 1
>   br i1 %obit, label %IfOverflow, label %IfNoOverflow
> IfOverflow:
>   ret i64 0
> IfNoOverflow:
>   ret i64 %val
> }
> ```
Indeed, this patch increases instructions in this case. I have to think about it.


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  https://reviews.llvm.org/D124374/new/

https://reviews.llvm.org/D124374