[llvm] dc0ae8c - [RISCV] Support VP_SETCC mask operations
Lian Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 28 01:53:01 PDT 2022
Author: Lian Wang
Date: 2022-04-28T08:52:29Z
New Revision: dc0ae8ce18227cf4a6774db3ebf086c5d711f78d
URL: https://github.com/llvm/llvm-project/commit/dc0ae8ce18227cf4a6774db3ebf086c5d711f78d
DIFF: https://github.com/llvm/llvm-project/commit/dc0ae8ce18227cf4a6774db3ebf086c5d711f78d.diff
LOG: [RISCV] Support VP_SETCC mask operations
Support VP_SETCC mask operations, turn it to logical operation.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D124438
Added:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0a7a48ee935f5..2b3fa1685db49 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -506,8 +506,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
VT, Expand);
}
- setOperationAction({ISD::VP_FPTOSI, ISD::VP_FPTOUI, ISD::VP_TRUNC}, VT,
- Custom);
+ setOperationAction(
+ {ISD::VP_FPTOSI, ISD::VP_FPTOUI, ISD::VP_TRUNC, ISD::VP_SETCC}, VT,
+ Custom);
}
for (MVT VT : IntVecVTs) {
@@ -3497,6 +3498,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_UITOFP:
return lowerVPFPIntConvOp(Op, DAG, RISCVISD::UINT_TO_FP_VL);
case ISD::VP_SETCC:
+ if (Op.getOperand(0).getSimpleValueType().getVectorElementType() == MVT::i1)
+ return lowerVPSetCCMaskOp(Op, DAG);
return lowerVPOp(Op, DAG, RISCVISD::SETCC_VL);
}
}
@@ -6099,6 +6102,85 @@ SDValue RISCVTargetLowering::lowerVPExtMaskOp(SDValue Op,
return convertFromScalableVector(VT, Result, DAG, Subtarget);
}
+SDValue RISCVTargetLowering::lowerVPSetCCMaskOp(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ MVT VT = Op.getSimpleValueType();
+
+ SDValue Op1 = Op.getOperand(0);
+ SDValue Op2 = Op.getOperand(1);
+ ISD::CondCode Condition = cast<CondCodeSDNode>(Op.getOperand(2))->get();
+ // NOTE: Mask is dropped.
+ SDValue VL = Op.getOperand(4);
+
+ MVT ContainerVT = VT;
+ if (VT.isFixedLengthVector()) {
+ ContainerVT = getContainerForFixedLengthVector(VT);
+ Op1 = convertToScalableVector(ContainerVT, Op1, DAG, Subtarget);
+ Op2 = convertToScalableVector(ContainerVT, Op2, DAG, Subtarget);
+ }
+
+ SDValue Result;
+ SDValue AllOneMask = DAG.getNode(RISCVISD::VMSET_VL, DL, ContainerVT, VL);
+
+ switch (Condition) {
+ default:
+ break;
+ // X != Y --> (X^Y)
+ case ISD::SETNE:
+ Result = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op1, Op2, VL);
+ break;
+ // X == Y --> ~(X^Y)
+ case ISD::SETEQ: {
+ SDValue Temp =
+ DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op1, Op2, VL);
+ Result =
+ DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Temp, AllOneMask, VL);
+ break;
+ }
+ // X >s Y --> X == 0 & Y == 1 --> ~X & Y
+ // X <u Y --> X == 0 & Y == 1 --> ~X & Y
+ case ISD::SETGT:
+ case ISD::SETULT: {
+ SDValue Temp =
+ DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op1, AllOneMask, VL);
+ Result = DAG.getNode(RISCVISD::VMAND_VL, DL, ContainerVT, Temp, Op2, VL);
+ break;
+ }
+ // X <s Y --> X == 1 & Y == 0 --> ~Y & X
+ // X >u Y --> X == 1 & Y == 0 --> ~Y & X
+ case ISD::SETLT:
+ case ISD::SETUGT: {
+ SDValue Temp =
+ DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op2, AllOneMask, VL);
+ Result = DAG.getNode(RISCVISD::VMAND_VL, DL, ContainerVT, Op1, Temp, VL);
+ break;
+ }
+ // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
+ // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
+ case ISD::SETGE:
+ case ISD::SETULE: {
+ SDValue Temp =
+ DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op1, AllOneMask, VL);
+ Result = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Temp, Op2, VL);
+ break;
+ }
+ // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
+ // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
+ case ISD::SETLE:
+ case ISD::SETUGE: {
+ SDValue Temp =
+ DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op2, AllOneMask, VL);
+ Result = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Temp, Op1, VL);
+ break;
+ }
+ }
+
+ if (!VT.isFixedLengthVector())
+ return Result;
+ return convertFromScalableVector(VT, Result, DAG, Subtarget);
+}
+
// Lower Floating-Point/Integer Type-Convert VP SDNodes
SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
unsigned RISCVISDOpc) const {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 29524197c392e..c4cf7c2b2e4af 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -652,6 +652,7 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
unsigned VecOpc) const;
SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
unsigned RISCVISDOpc) const;
SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
new file mode 100644
index 0000000000000..4346acfdafd44
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
@@ -0,0 +1,414 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK
+
+
+declare <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1>, <2 x i1>, metadata, <2 x i1>, i32)
+
+define <2 x i1> @icmp_eq_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"eq", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+declare <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1>, <4 x i1>, metadata, <4 x i1>, i32)
+
+define <4 x i1> @icmp_eq_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"eq", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+declare <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1>, <8 x i1>, metadata, <8 x i1>, i32)
+
+define <8 x i1> @icmp_eq_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"eq", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+declare <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1>, <16 x i1>, metadata, <16 x i1>, i32)
+
+define <16 x i1> @icmp_eq_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"eq", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_ne_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"ne", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_ne_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"ne", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_ne_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"ne", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_ne_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"ne", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_slt_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"slt", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_slt_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"slt", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_slt_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"slt", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_slt_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"slt", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_ult_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"ult", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_ult_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"ult", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_ult_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_ult_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"ult", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_sgt_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"sgt", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_sgt_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"sgt", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_sgt_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"sgt", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_sgt_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"sgt", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_ugt_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"ugt", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_ugt_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"ugt", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_ugt_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_ugt_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"ugt", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_sle_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"sle", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_sle_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"sle", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_sle_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"sle", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_sle_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"sle", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_ule_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"ule", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_ule_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"ule", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_ule_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_ule_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"ule", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_sge_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"sge", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_sge_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"sge", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_sge_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"sge", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_sge_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"sge", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
+
+define <2 x i1> @icmp_uge_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"uge", <2 x i1> %m, i32 %evl)
+ ret <2 x i1> %v
+}
+
+define <4 x i1> @icmp_uge_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"uge", <4 x i1> %m, i32 %evl)
+ ret <4 x i1> %v
+}
+
+define <8 x i1> @icmp_uge_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
+ ret <8 x i1> %v
+}
+
+define <16 x i1> @icmp_uge_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"uge", <16 x i1> %m, i32 %evl)
+ ret <16 x i1> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
new file mode 100644
index 0000000000000..cc61ce977cd08
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
@@ -0,0 +1,719 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK
+
+declare <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, metadata, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i1> @icmp_eq_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"eq", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+declare <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, metadata, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x i1> @icmp_eq_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"eq", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+declare <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, metadata, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x i1> @icmp_eq_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"eq", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+declare <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, metadata, <vscale x 8 x i1>, i32)
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"eq", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+declare <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, metadata, <vscale x 16 x i1>, i32)
+
+define <vscale x 16 x i1> @icmp_eq_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"eq", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+declare <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, metadata, <vscale x 32 x i1>, i32)
+
+define <vscale x 32 x i1> @icmp_eq_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"eq", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+declare <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, metadata, <vscale x 64 x i1>, i32)
+
+define <vscale x 64 x i1> @icmp_eq_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_eq_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"eq", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_ne_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"ne", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_ne_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"ne", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_ne_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"ne", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"ne", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_ne_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"ne", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_ne_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"ne", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_ne_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ne_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"ne", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_slt_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"slt", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_slt_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"slt", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_slt_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"slt", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"slt", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_slt_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"slt", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_slt_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"slt", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_slt_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_slt_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"slt", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_ult_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_ult_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"ult", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_ult_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"ult", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_ult_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"ult", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_ult_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"ult", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_ult_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ult_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"ult", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_sgt_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"sgt", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_sgt_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"sgt", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_sgt_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"sgt", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"sgt", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_sgt_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"sgt", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_sgt_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"sgt", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_sgt_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sgt_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"sgt", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_ugt_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_ugt_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"ugt", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_ugt_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"ugt", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_ugt_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"ugt", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_ugt_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"ugt", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_ugt_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ugt_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmandn.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"ugt", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_sle_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_sle_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"sle", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_sle_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"sle", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"sle", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_sle_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"sle", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_sle_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"sle", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_sle_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sle_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"sle", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_ule_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_ule_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"ule", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_ule_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"ule", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_ule_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"ule", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_ule_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"ule", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_ule_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_ule_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"ule", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_sge_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"sge", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_sge_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"sge", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_sge_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"sge", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"sge", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_sge_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"sge", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_sge_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"sge", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_sge_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_sge_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"sge", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
+
+define <vscale x 1 x i1> @icmp_uge_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %v
+}
+
+define <vscale x 2 x i1> @icmp_uge_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 2 x i1> @llvm.vp.icmp.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, metadata !"uge", <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %v
+}
+
+define <vscale x 4 x i1> @icmp_uge_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i1> @llvm.vp.icmp.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, metadata !"uge", <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %v
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %v
+}
+
+define <vscale x 16 x i1> @icmp_uge_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i1> @llvm.vp.icmp.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, metadata !"uge", <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %v
+}
+
+define <vscale x 32 x i1> @icmp_uge_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x i1> @llvm.vp.icmp.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, metadata !"uge", <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %v
+}
+
+define <vscale x 64 x i1> @icmp_uge_vv_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: icmp_uge_vv_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT: vmxnor.mm v0, v8, v0
+; CHECK-NEXT: ret
+ %v = call <vscale x 64 x i1> @llvm.vp.icmp.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, metadata !"uge", <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %v
+}
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