[PATCH] D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

[Guozhi Wei via Phabricator via llvm-commits]

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Add a new pattern A - (B + C)  ==>  (A - B) - C  to give machine combiner a chance to evaluate which instruction sequence has lower latency.

This patch also contains improvement to MachineCombiner's cost model, so its computation of critical path  length is more precise.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124564

Files:
  llvm/include/llvm/CodeGen/MachineCombinerPattern.h
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/addsub_ext.ll
  llvm/test/CodeGen/AArch64/arm64-fma-combines.ll
  llvm/test/CodeGen/AArch64/fadd-combines.ll
  llvm/test/CodeGen/AArch64/i128-math.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/machine-combiner-subadd.ll
  llvm/test/CodeGen/AArch64/madd-combiner.ll
  llvm/test/CodeGen/AArch64/madd-lohi.ll
  llvm/test/CodeGen/AArch64/mul-lohi.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll

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