[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

Wed Apr 27 06:51:13 PDT 2022

dmgreen added a comment.

Can you pull the cttz code into a new function, so that it is a little more separate from the other code in performCSELCombine.

Running clang-format on the patch can also be good to remove all the formatting issues. There is a script to help in clang/tools/clang-format/clang-format-diff.py.

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17478
+        (CTTZ.getOpcode() == ISD::TRUNCATE &&
+          CTTZ.getOperand(0).getOpcode() == ISD::CTTZ))) {
+    if (isNullConstant(Zero) &&
----------------
craig.topper wrote:
> Technically, if you look through a truncate you need to know the truncate didn't drop any bits of the CTTZ result. But maybe AArch64ISD::SUBS and CSEL can only be created after type legalization so the only possible types are i32 and i64? I'm not an AArch64 expert so I don't know.
Yeah I believe SUBS and CSEL will only be generated for legal types. Perhaps it is worth adding an assert just to be safe.

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  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782