[PATCH] D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs
Christudasan Devadasan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 27 03:53:54 PDT 2022
cdevadas added inline comments.
================
Comment at: llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir:194
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc
+ ; GCN-NEXT: {{ $}}
----------------
cdevadas wrote:
> arsenm wrote:
> > Needs a case where the insert block has no terminators
> I couldn't write one successfully. Will try some unstructured flow to force one.
I don't think such a case exists. A fall-through block will have only one successor and that becomes the nearest dominator for its children.
It would be true even for any unstructured flow.
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https://reviews.llvm.org/D124196/new/
https://reviews.llvm.org/D124196
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