[PATCH] D124438: [RISCV] Support VP_SETCC mask operations

[WangLian via Phabricator via llvm-commits]

Jimerlife marked an inline comment as done.
Jimerlife added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6289
+  }
+  case ISD::SETLT:
+  case ISD::SETULT: {
----------------
craig.topper wrote:
> I don't think these are correct. Here's the equivalent code for regular setcc
> 
> ```
>     case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
>     case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
>       Temp = DAG.getNOT(dl, N0, OpVT);
>       N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
>       if (!DCI.isCalledByLegalizer())
>         DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
>     case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
>       Temp = DAG.getNOT(dl, N1, OpVT);
>       N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
>       if (!DCI.isCalledByLegalizer())
>         DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
>     case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
>       Temp = DAG.getNOT(dl, N0, OpVT);
>       N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
>       if (!DCI.isCalledByLegalizer())
>         DCI.AddToWorklist(Temp.getNode());
>       break;
>     case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
>     case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
>       Temp = DAG.getNOT(dl, N1, OpVT);
>       N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
>       break;
>     }
> ```
I have adjusted code according to regular setcc. Thanks for your advice.


Repository:
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  https://reviews.llvm.org/D124438/new/

https://reviews.llvm.org/D124438