[llvm] bcb2b86 - [RISCV] Precommit test for D121881

[ShihPo Hung via llvm-commits]

Author: ShihPo Hung
Date: 2022-04-26T20:14:54-07:00
New Revision: bcb2b86df672c0c7779c070000c3d4cdab6017bb

URL: https://github.com/llvm/llvm-project/commit/bcb2b86df672c0c7779c070000c3d4cdab6017bb
DIFF: https://github.com/llvm/llvm-project/commit/bcb2b86df672c0c7779c070000c3d4cdab6017bb.diff

LOG: [RISCV] Precommit test for D121881

Differential Revision: https://reviews.llvm.org/D123385

Added: 
    llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll b/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
new file mode 100644
index 0000000000000..8d06ece64a7d7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(iXLen);
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+; Use unmasked instruction because the mask operand is allone mask
+define <vscale x 1 x i8> @test0(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: test0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
+    iXLen %2);
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i1> %allone,
+    iXLen %2, iXLen 1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+; FIXME: Use an unmasked TAIL_AGNOSTIC instruction if the tie operand is IMPLICIT_DEF
+define <vscale x 1 x i8> @test1(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, tu, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
+    iXLen %2);
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i1> %allone,
+    iXLen %2, iXLen 0)
+
+  ret <vscale x 1 x i8> %a
+}
+
+; FIXME: Use an unmasked TU instruction because of the policy operand
+define <vscale x 1 x i8> @test2(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, tu, mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
+    iXLen %3);
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %allone,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i8> %a
+}
+
+; Merge operand is dropped because of the policy operand
+define <vscale x 1 x i8> @test3(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
+    iXLen %3);
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %allone,
+    iXLen %3, iXLen 1)
+
+  ret <vscale x 1 x i8> %a
+}