[PATCH] D124325: [AArch64][SVE] Support logical operation BIC with DestructiveBinary patterns

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

I don't think either of these are good options.  I don't like the idea of having instruction specific handling within the expand code and I'm not sure where the logic from (2) comes from but regardless using `earlyclobber` in this way will force `Dst` to be unique and thus forces the need for `movpfrx` (i.e. it blocks the `BIC_ZPZZ_ZERO A, P, A, B` use case ).

To my mind the best option is to allow the register requires to be better expressed as part of the pseudo instruction.  Until then I cannot see how we can move this feature out of its experimental phase.  Perhaps there's an alternative to D88595 <https://reviews.llvm.org/D88595> but I've not thought about it for a while.  How important is `movpfrx` based zeroing to you right now? Have you got a problematic use case you can share?


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https://reviews.llvm.org/D124325