[PATCH] D124464: [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17773
+  if (SDNode *Generic = DCI.DAG.getNodeIfExists(
+          GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS}))
+    DCI.CombineTo(Generic, SDValue(N, 0));
----------------
Should this be `{N->ops()}` to support the `ADC` case? Is it possible to write tests for the new opcode cases?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18790-18793
+  case AArch64ISD::ADDS:
+    return performFlagSettingCombine(N, DCI, ISD::ADD);
+  case AArch64ISD::SUBS:
+    return performFlagSettingCombine(N, DCI, ISD::SUB);
----------------
Do the `ADDS` and `SUBS` cases occur today? If they do then can we have some tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124464/new/

https://reviews.llvm.org/D124464