[PATCH] D122672: [CodeGen][ARM] Enable Swing Module Scheduling for ARM

[David Penry via Phabricator via llvm-commits]

dpenry added inline comments.


================
Comment at: llvm/lib/CodeGen/MachinePipeliner.cpp:2792
             return false;
+          if (InstrToCycle[SI.getSUnit()] == CycleDef)
+            return false;
----------------
JanekvO wrote:
> Is it possible to get an ordering where a use is scheduled prior to the `CycleDef`?
It shouldn't be possible.

When dependence latencies are greater than zero, schedulePipeline only assigns uses after deps in the full, uncollapsed schedule. When they are zero, it might assign them to the same cycle and get them in the wrong order -- if it assigns them to a different cycle they won't be wrong.  The collapsing of the schedule can introduce misorderings when the use and def are not in the same stage.  orderDependence fixes both of these cases for virtual registers, but not physical registers.  The first test here  reports any cross-stage physical register use/def as invalid, thus conservatively taking care of problems caused when collapsing.  The second test reports same-cycle/same-stage use/def pairs as invalid, thus conservatively taking care of problems in the original ordering.

There wouldn't be anything wrong with making this a <= check just to be sure -- and it would be more resilient to changes in other parts of the code -- so I'll go ahead and do that.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122672/new/

https://reviews.llvm.org/D122672