[PATCH] D124267: [MachinePipeliner] Fix unscheduled instruction

Jinsong Ji via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 26 08:00:54 PDT 2022


jsji added a comment.

In D124267#3468434 <https://reviews.llvm.org/D124267#3468434>, @thopre wrote:

> Adding @jsji to review the changes to PowerPC testcases. I've checked the MIR after the pipeliner for sms-phi-3.ll and the loop still gets pipelined (which makes sense since the modified code executes after the decision to pipeline is made) but the code gets simplified by later pass. Are you happy with the change?

Thanks for notifying me. I am OK as long as the `loop still gets pipelined `.  We can look into why the code gets simplified by later pass and maybe improve the testcase later.
So, feel free to commit once you address the comments from Brendon.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124267/new/

https://reviews.llvm.org/D124267



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