[PATCH] D124455: [X86] Check the address in machine verifier

[Kan Shengchen via Phabricator via llvm-commits]

skan updated this revision to Diff 425217.
skan marked an inline comment as done.
skan added a comment.

Remove redundant IR/MIR in the test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124455/new/

https://reviews.llvm.org/D124455

Files:
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir


Index: llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
@@ -0,0 +1,29 @@
+# RUN: not --crash llc -march=x86-64 -run-pass none -opaque-pointers -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that the address is checked in machine verifier.
+
+---
+name:            baz
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $rdi, $xmm0
+  
+    %1:vr128 = COPY $xmm0
+    %0:gr64 = COPY $rdi
+    %2:vr128 = COPY %1
+  
+  bb.1:
+    successors: %bb.1(0x80000000)
+  
+    %3:vr256 = AVX_SET0
+    %4:vr128 = VPSLLDri %2, 31
+    %5:vr256 = VPMOVSXDQYrr killed %4
+    %8:vr256 = IMPLICIT_DEF
+    ; CHECK: *** Bad machine code: Scale factor in address must be 1, 2, 4 or 8 ***
+    %6:vr256, %7:vr256 = VGATHERQPDYrm %3, %0, 16, killed %8, 0, $noreg, %5 :: (load unknown-size, align 8)
+    %9:vr128 = COPY %6.sub_xmm
+    ; CHECK: *** Bad machine code: Displacement in address must fit into 32-bit signed integer ***
+    VMOVLPDmr $noreg, 1, $noreg, 1111111111111, $noreg, killed %9 :: (store (s64) into `ptr null`)
+
+...
Index: llvm/lib/Target/X86/X86InstrInfo.h
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.h
+++ llvm/lib/Target/X86/X86InstrInfo.h
@@ -562,6 +562,8 @@
                      MachineBasicBlock::iterator &It, MachineFunction &MF,
                      outliner::Candidate &C) const override;
 
+  bool verifyInstruction(const MachineInstr &MI,
+                         StringRef &ErrInfo) const override;
 #define GET_INSTRINFO_HELPER_DECLS
 #include "X86GenInstrInfo.inc"
 
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3619,6 +3619,33 @@
   return AM;
 }
 
+bool X86InstrInfo::verifyInstruction(const MachineInstr &MI,
+                                     StringRef &ErrInfo) const {
+  Optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MI, nullptr);
+  if (!AMOrNone)
+    return true;
+
+  ExtAddrMode AM = *AMOrNone;
+
+  switch (AM.Scale) {
+  case 1:
+  case 2:
+  case 4:
+  case 8:
+    break;
+  default:
+    ErrInfo = "Scale factor in address must be 1, 2, 4 or 8";
+    return false;
+  }
+  if (!isInt<32>(AM.Displacement)) {
+    ErrInfo = "Displacement in address must fit into 32-bit signed "
+              "integer";
+    return false;
+  }
+
+  return true;
+}
+
 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
                                            const Register Reg,
                                            int64_t &ImmVal) const {


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