[PATCH] D124424: [RISCV] Fix alias print for vmnot.m

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: khchen, kito-cheng, frasercrmck, rogfer01.
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By clearing the HasDummyMask flag from mask register binary operations.

This was causing an extra operand to get appended between when
converting from MachineInstr to MCInst. This extra operand doesn't
appear in the assembly string so was mostly ignored, but it prevented
the alias instruction printing from working correctly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124424

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

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