[PATCH] D123394: [CodeGen] Late cleanup of redundant address/immediate definitions.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 424998.
jonpa added a reviewer: arsenm.
jonpa added a comment.
Herald added subscribers: kerbowa, wdng, jvesely.

AMDGPU tests updated.

Some test updates I did not understand: 's_waitcnt_depctr 0xffe3' removed in cc-update.ll, flat-scratch.ll, ... . 's_clause 0x1' added in chain-hi-to-lo.ll..?

How do I update test/CodeGen/AMDGPU/multilevel-break.ll?
For the opt line, I get
../llvm/utils/update_test_checks.py --opt-binary ./bin/opt ../llvm/test/CodeGen/AMDGPU/multilevel-break.ll

WARNING: Skipping non-opt RUN line: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
WARNING: Change IR value name 'tmp43' or use --prefix-filecheck-ir-name to prevent possible conflict with scripted FileCheck name.
...
And for llc line, I get
../llvm/utils/update_llc_test_checks.py --llc-binary ./bin/llc ../llvm/test/CodeGen/AMDGPU/multilevel-break.ll
WARNING: Skipping test which wasn't autogenerated by utils/update_llc_test_checks.py: ../llvm/test/CodeGen/AMDGPU/multilevel-break.ll


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123394/new/

https://reviews.llvm.org/D123394

Files:
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/test/CodeGen/AArch64/framelayout-sve.mir
  llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.mir
  llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
  llvm/test/CodeGen/AMDGPU/cc-update.ll
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
  llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
  llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
  llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
  llvm/test/CodeGen/ARM/machine-outliner-calls.mir
  llvm/test/CodeGen/ARM/reg_sequence.ll
  llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
  llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
  llvm/test/CodeGen/Mips/llvm-ir/shl.ll
  llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
  llvm/test/CodeGen/PowerPC/cgp-select.ll
  llvm/test/CodeGen/PowerPC/fast-isel-branch.ll
  llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
  llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/SystemZ/frame-28.mir
  llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll
  llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
  llvm/test/CodeGen/X86/AMX/amx-across-func.ll
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
  llvm/test/CodeGen/X86/masked_load.ll
  llvm/test/CodeGen/X86/oddshuffles.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/vec_shift5.ll
  llvm/test/CodeGen/XCore/scavenging.ll

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