[PATCH] D124374: [RISCV][TargetLowering] Special case overflow expansion for (uaddo X, C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:8823
   SDValue SetCC;
-  if (IsAdd && isOneConstant(RHS)) {
-    // Special case: uaddo X, 1 overflowed if X+1 is 0. This potential reduces
-    // the live range of X. We assume comparing with 0 is cheap.
-    // TODO: This generalizes to (X + C) < C.
-    SetCC =
-        DAG.getSetCC(dl, SetCCType, Result,
-                     DAG.getConstant(0, dl, Node->getValueType(0)), ISD::SETEQ);
+  if (IsAdd && isa<ConstantSDNode>(RHS)) {
+    // Special case: uaddo X, C overflowed if X+C < C. This potential reduces
----------------
Do we have any tests where RHS is a constant, but not a simm12 and needs to be placed in a register.

Would also be good to test cases where the setcc result is used by a branch. Even a simm12 would need to be put in a register for that case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124374/new/

https://reviews.llvm.org/D124374