[PATCH] D92105: [RISCV] Add pre-emit pass to make more instructions compressible

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 424881.
lewis-revill added a comment.

Rebased including an update from using `isShiftedUIntN` to the templated replacement `isShiftedUInt<N, S>`. Addressed the issue of inserting incorrect instructions to copy FP registers to compressible FP registers by using `FSGNJ_S` and `FSGNJ_D` instead. We note that we can't have an additional offset to adjust the resulting register by if it is an FP register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92105/new/

https://reviews.llvm.org/D92105

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/make-compressible-rv64.mir
  llvm/test/CodeGen/RISCV/make-compressible.mir

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