[PATCH] D123991: [LangRef] Clarify load/store of non-byte-sized types

[Nuno Lopes via Phabricator via llvm-commits]

nlopes added a comment.

> In D123991#3466373 <https://reviews.llvm.org/D123991#3466373>, @aqjune wrote:
>
>> In D123991#3464364 <https://reviews.llvm.org/D123991#3464364>, @nlopes wrote:
>>
>>> Well, here we are discussing the semantics of LLVM IR. It's ok for the semantics of SDAG to be different, as long as it's a refinement of LLVM IR's.
>>
>> I think any valid compilation of LLVM IR should be considered here.
>> There might be another compiler for LLVM IR that does not use SDAG internally. If padding is poison, it is valid for the other compiler to lower padding to non-zero bits, which will invalidate the transformations in various machines mentioned above.

That's fine, as long as you don't mix compiled files between those 2 compilers. But that's about the ABI, not the semantics of LLVM IR. Per Roman's comment, the layout is target specific, so we cannot define at the IR level.
Load/store with different types is not well-defined, so padding cannot be observed at IR level (usually). The only concern is load widening, but that's fixed with the byte type, and padding doesn't make the problem worse.

In D123991#3467006 <https://reviews.llvm.org/D123991#3467006>, @nikic wrote:

>   define i8 @test(ptr %p) {
>     store i8 -1, ptr %p
>     %v = load i1, ptr %p
>     %r = zext i1 %v to i8
>     ret i8 %r
>   }

I think we consider this example invalid as the store/load pair has different types.

In D123991#3467043 <https://reviews.llvm.org/D123991#3467043>, @lebedev.ri wrote:

> As for `i1`, you have seen enum BooleanContent <https://github.com/llvm/llvm-project/blob/15650b320bf6a1ce5b7e00147d1cf2725946aab2/llvm/include/llvm/CodeGen/TargetLowering.h#L229-L234>, correct?

Ah nice. That shows that the memory layout for i1 is target-specific.
It's easier if we define the padding as poison + load/store type mismatch as poison as well.


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