[PATCH] D123978: [RISCV] Support getHostCpuName for sifive-u74

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Support/Host.cpp:383-401
+StringRef sys::detail::getHostCPUNameForRISCV(StringRef ProcCpuinfoContent) {
+  // There are 24 lines in /proc/cpuinfo
+  SmallVector<StringRef, 24> Lines;
+  ProcCpuinfoContent.split(Lines, "\n");
+
+  // Look for uarch line to determine cpu name
+  StringRef UArch;
----------------
StephenFan wrote:
> luismarques wrote:
> > StephenFan wrote:
> > > luismarques wrote:
> > > > It seems a bit silly to allocate memory for all the line references if we are only going to care about one of them. Do you expect we'll need some of the other lines as well in the future?
> > > Yes, I think we will have more and more RISC-V development boards in the future. 
> > And those other boards can't be recognized from the uarch line?
> I think they can. But I don't have those boards currently.
I've confirmed with my colleague, `sifive,u74-mc` is right, and he suggest we should recognize `sifive,bullet0`[1] too, because that what upstream linux use, and `sifive,u74-mc` are used in SiFive's OpenEmbedded release[2].

[1] https://github.com/torvalds/linux/blob/master/arch/riscv/boot/dts/sifive/fu740-c000.dtsi#L42
[2] https://github.com/sifive/meta-sifive/blob/2022.03/recipes-kernel/linux/files/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123978/new/

https://reviews.llvm.org/D123978