[llvm] 6fa1d12 - ProcessImplicitDefs: Use required properties instead of isSSA assert

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-04-22T18:28:45-04:00
New Revision: 6fa1d12b3ca7665cf5cc20682ccd5d62a00b58ed

URL: https://github.com/llvm/llvm-project/commit/6fa1d12b3ca7665cf5cc20682ccd5d62a00b58ed
DIFF: https://github.com/llvm/llvm-project/commit/6fa1d12b3ca7665cf5cc20682ccd5d62a00b58ed.diff

LOG: ProcessImplicitDefs: Use required properties instead of isSSA assert

Added: 
    

Modified: 
    llvm/lib/CodeGen/ProcessImplicitDefs.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index 117ee59ac239a..7327f9e52efc3 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -46,6 +46,11 @@ class ProcessImplicitDefs : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &au) const override;
 
   bool runOnMachineFunction(MachineFunction &MF) override;
+
+  virtual MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::IsSSA);
+  }
 };
 } // end anonymous namespace
 
@@ -141,7 +146,6 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
-  assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
   assert(WorkList.empty() && "Inconsistent worklist state");
 
   for (MachineBasicBlock &MBB : MF) {