[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic updated this revision to Diff 424563.
rahular-rrlogic added a comment.

Removed hard coded constants and replaced that with bitwidth, added full support for i64 and added more conditions to match against the intended pattern. Modified test to include cases in which the optimization does not take place.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/table-based-cttz.ll

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