[PATCH] D124247: [Trivial Dead] Consider any non volatile load as trivially dead independent on ordering

[Serguei Katkov via Phabricator via llvm-commits]

skatkov added a comment.

In D124247#3468179 <https://reviews.llvm.org/D124247#3468179>, @efriedma wrote:

> This isn't trivially correct.
>
> For example, say you have a sequence "%load1 = load seq_cst %a; %load2 = load relaxed %a".  I think the later load can sort of "inherit" the sequential consistency of the earlier load; the values it can contain are restricted.   (I mean, maybe I'm missing something, but it's not as simple as "no one will check what actually value has been read".)

I'm sorry I do not follow your example. First of all read the same memory as atomic and as not an atomic generally is not a good idea, however...

If in real execution we have an order load1, store-release in other thread, load2 then load2 does not introduce any release-acquire synchronization. So it would be incorrect to say about any inheritance.
May be I miss anything as well....


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