[PATCH] D124224: [AArch64][SVE] Add some logical operation DestructiveBinaryComm patterns

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:2776
+  def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>,
+             SVEPseudo2Instr<Ps # _B, 1>, SVEInstr2Rev<NAME # _B, revname # _B, isOrig>;
+  def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>,
----------------
Allen wrote:
> david-arm wrote:
> > Again, I don't think we need any of these for the logical operations.
> Thanks very much , can you help to detailly point out  what's "these" ? I may don't get your idea?
Sorry I wasn't being very clear - I was relying upon my comment highlighting the right part of the code! I just mean that the ", SVEInstr2Rev<...>" bits are unnecessary I think? We don't have any reverse logical operations so perhaps we can just delete it? If so, you can also just delete the 'revname' and 'isOrig' arguments passed to the multiclass as well.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124224/new/

https://reviews.llvm.org/D124224