[llvm] 2147b6c - [AMDGPU] Remove no-ret atomic ops selection in the post-isel hook

[Abinav Puthan Purayil via llvm-commits]

Author: Abinav Puthan Purayil
Date: 2022-04-22T09:37:41+05:30
New Revision: 2147b6c89d440eea047f27f4c01130e1b6528591

URL: https://github.com/llvm/llvm-project/commit/2147b6c89d440eea047f27f4c01130e1b6528591
DIFF: https://github.com/llvm/llvm-project/commit/2147b6c89d440eea047f27f4c01130e1b6528591.diff

LOG: [AMDGPU] Remove no-ret atomic ops selection in the post-isel hook

No-ret atomic ops are now selected in tblgen.

Differential Revision: https://reviews.llvm.org/D124086

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index bd24364c35989..ec922ce6632ce 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11698,47 +11698,6 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
     return;
   }
 
-  // Replace unused atomics with the no return version.
-  int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode());
-  if (NoRetAtomicOp != -1) {
-    if (!Node->hasAnyUseOfValue(0)) {
-      int CPolIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
-                                               AMDGPU::OpName::cpol);
-      if (CPolIdx != -1) {
-        MachineOperand &CPol = MI.getOperand(CPolIdx);
-        CPol.setImm(CPol.getImm() & ~AMDGPU::CPol::GLC);
-      }
-      MI.removeOperand(0);
-      MI.setDesc(TII->get(NoRetAtomicOp));
-      return;
-    }
-
-    // For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
-    // instruction, because the return type of these instructions is a vec2 of
-    // the memory type, so it can be tied to the input operand.
-    // This means these instructions always have a use, so we need to add a
-    // special case to check if the atomic has only one extract_subreg use,
-    // which itself has no uses.
-    if ((Node->hasNUsesOfValue(1, 0) &&
-         Node->use_begin()->isMachineOpcode() &&
-         Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
-         !Node->use_begin()->hasAnyUseOfValue(0))) {
-      Register Def = MI.getOperand(0).getReg();
-
-      // Change this into a noret atomic.
-      MI.setDesc(TII->get(NoRetAtomicOp));
-      MI.removeOperand(0);
-
-      // If we only remove the def operand from the atomic instruction, the
-      // extract_subreg will be left with a use of a vreg without a def.
-      // So we need to insert an implicit_def to avoid machine verifier
-      // errors.
-      BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
-              TII->get(AMDGPU::IMPLICIT_DEF), Def);
-    }
-    return;
-  }
-
   if (TII->isMIMG(MI) && !MI.mayStore())
     AddIMGInit(MI);
 }