[PATCH] D124222: [RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+ADDI. Because ADDI uses a sign
extended constant, it's possible that after subtracting it out, we
end up with a simm32 that maps to LUI.

This patch detects this case after removing Lo12 and before shifting
the value for SLLI.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124222

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
  llvm/test/CodeGen/RISCV/imm.ll
  llvm/test/CodeGen/RISCV/rv64zbs.ll

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