[PATCH] D124182: [AMDGPU] Combine DPP mov even if old reg def is in different BB

[Jay Foad via Phabricator via llvm-commits]

foad added a subscriber: cwabbott.
foad added a comment.

In D124182#3465094 <https://reviews.llvm.org/D124182#3465094>, @arsenm wrote:

> The worry is changes in exec between the def and the use

I don't get it. The full sequence is something like this:

  %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec // A
  ...
  %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec // B
  ...
  %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec // C

A sets up the value to be used when reading inactive lanes, which will either be don't-care or must be an identity for the operation done in C.

I can kind of understand that exec changes between B and C might be a problem. That is what @cwabbott called out in D55314#1321303 <https://reviews.llvm.org/D55314#1321303>, and @vpykhtin added a check for in D55444 <https://reviews.llvm.org/D55444>. But they also added a check for A and B being in the same BB.

If we're in SSA form then the only exec change that makes sense between A and B is narrowing the exec mask, as if B was inside the body of an "if", and that does not change the fact that B uses the constant value defined by A. I don't see how this can go wrong.


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