[PATCH] D123956: [AMDGPU] Refine 64 bit misaligned LDS ops selection

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 21 09:37:26 PDT 2022


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGac94073daa18: [AMDGPU] Refine 64 bit misaligned LDS ops selection (authored by rampitec).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123956/new/

https://reviews.llvm.org/D123956

Files:
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/ds_read2.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D123956.424237.patch
Type: text/x-patch
Size: 7002 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220421/c8a13749/attachment.bin>


More information about the llvm-commits mailing list