[llvm] 4e0dacb - AMDGPU/GlobalISel: Precommit test for D124163
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 21 07:12:41 PDT 2022
Author: Petar Avramovic
Date: 2022-04-21T16:12:03+02:00
New Revision: 4e0dacb2cf325158c3c672f45202ab166aec99b0
URL: https://github.com/llvm/llvm-project/commit/4e0dacb2cf325158c3c672f45202ab166aec99b0
DIFF: https://github.com/llvm/llvm-project/commit/4e0dacb2cf325158c3c672f45202ab166aec99b0.diff
LOG: AMDGPU/GlobalISel: Precommit test for D124163
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
new file mode 100644
index 0000000000000..849e18ee8745f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=WAVE64 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=WAVE32 %s
+
+define amdgpu_ps void @i1_vcc_to_vcc_copy(i32 %val, float %a0, float %a1, float %b0, float %b1) {
+; WAVE64-LABEL: i1_vcc_to_vcc_copy:
+; WAVE64: ; %bb.0: ; %main_body
+; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
+; WAVE64-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; WAVE64-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
+; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm
+; WAVE64-NEXT: s_endpgm
+;
+; WAVE32-LABEL: i1_vcc_to_vcc_copy:
+; WAVE32: ; %bb.0: ; %main_body
+; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
+; WAVE32-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; WAVE32-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm
+; WAVE32-NEXT: s_endpgm
+main_body:
+ %vcc = icmp eq i32 %val, 2
+ %a = select i1 %vcc, float %a0, float %a1
+ %b = select i1 %vcc, float %b0, float %b1
+ call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true)
+ ret void
+}
+
+define amdgpu_ps void @i1_sgpr_to_vcc_copy(i32 inreg %val, float %a0, float %a1, float %b0, float %b1) {
+; WAVE64-LABEL: i1_sgpr_to_vcc_copy:
+; WAVE64: ; %bb.0: ; %main_body
+; WAVE64-NEXT: s_cmp_eq_u32 s0, 2
+; WAVE64-NEXT: s_cselect_b32 s0, 1, 0
+; WAVE64-NEXT: s_and_b32 s0, 1, s0
+; WAVE64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; WAVE64-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm
+; WAVE64-NEXT: s_endpgm
+;
+; WAVE32-LABEL: i1_sgpr_to_vcc_copy:
+; WAVE32: ; %bb.0: ; %main_body
+; WAVE32-NEXT: s_cmp_eq_u32 s0, 2
+; WAVE32-NEXT: s_cselect_b32 vcc_lo, 1, 0
+; WAVE32-NEXT: s_and_b32 s0, 1, vcc_lo
+; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; WAVE32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; WAVE32-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm
+; WAVE32-NEXT: s_endpgm
+main_body:
+ %uniform_i1 = icmp eq i32 %val, 2
+ %a = select i1 %uniform_i1, float %a0, float %a1
+ %b = select i1 %uniform_i1, float %b0, float %b1
+ call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true)
+ ret void
+}
+
+declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
new file mode 100644
index 0000000000000..bf68ae2a5ebd3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
@@ -0,0 +1,139 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=WAVE64
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=WAVE32
+
+---
+name: i1_vcc_to_vcc_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+
+ ; WAVE64-LABEL: name: i1_vcc_to_vcc_copy
+ ; WAVE64: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+ ; WAVE64-NEXT: {{ $}}
+ ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; WAVE64-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; WAVE64-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; WAVE64-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; WAVE64-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2
+ ; WAVE64-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY5]], implicit $exec
+ ; WAVE64-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; WAVE64-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY4]], 0, [[COPY3]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; WAVE64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE64-NEXT: EXP_DONE 0, [[V_CNDMASK_B32_e64_]], [[V_CNDMASK_B32_e64_1]], [[COPY6]], [[COPY7]], -1, 0, 15, implicit $exec
+ ; WAVE64-NEXT: S_ENDPGM 0
+ ; WAVE32-LABEL: name: i1_vcc_to_vcc_copy
+ ; WAVE32: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+ ; WAVE32-NEXT: {{ $}}
+ ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; WAVE32-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; WAVE32-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; WAVE32-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; WAVE32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2
+ ; WAVE32-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY5]], implicit $exec
+ ; WAVE32-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; WAVE32-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY4]], 0, [[COPY3]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; WAVE32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE32-NEXT: EXP_DONE 0, [[V_CNDMASK_B32_e64_]], [[V_CNDMASK_B32_e64_1]], [[COPY6]], [[COPY7]], -1, 0, 15, implicit $exec
+ ; WAVE32-NEXT: S_ENDPGM 0
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = COPY $vgpr3
+ %4:vgpr(s32) = COPY $vgpr4
+ %5:sgpr(s32) = G_IMPLICIT_DEF
+ %6:sgpr(s32) = G_CONSTANT i32 2
+ %7:vgpr(s32) = COPY %6(s32)
+ %8:vcc(s1) = G_ICMP intpred(eq), %0(s32), %7
+ %9:vgpr(s32) = G_SELECT %8(s1), %1, %2
+ %10:vgpr(s32) = G_SELECT %8(s1), %3, %4
+ %11:vgpr(s32) = COPY %5(s32)
+ %12:vgpr(s32) = COPY %5(s32)
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, %9(s32), %10(s32), %11(s32), %12(s32), -1, -1
+ S_ENDPGM 0
+...
+
+---
+name: i1_sgpr_to_vcc_copy
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+ ; WAVE64-LABEL: name: i1_sgpr_to_vcc_copy
+ ; WAVE64: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; WAVE64-NEXT: {{ $}}
+ ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; WAVE64-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; WAVE64-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; WAVE64-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2
+ ; WAVE64-NEXT: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; WAVE64-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $scc
+ ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY5]], implicit-def $scc
+ ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
+ ; WAVE64-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
+ ; WAVE64-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY5]], implicit-def $scc
+ ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_1]], implicit $exec
+ ; WAVE64-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY4]], 0, [[COPY3]], [[V_CMP_NE_U32_e64_1]], implicit $exec
+ ; WAVE64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE64-NEXT: EXP_DONE 0, [[V_CNDMASK_B32_e64_]], [[V_CNDMASK_B32_e64_1]], [[COPY6]], [[COPY7]], -1, 0, 15, implicit $exec
+ ; WAVE64-NEXT: S_ENDPGM 0
+ ; WAVE32-LABEL: name: i1_sgpr_to_vcc_copy
+ ; WAVE32: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; WAVE32-NEXT: {{ $}}
+ ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; WAVE32-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; WAVE32-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; WAVE32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2
+ ; WAVE32-NEXT: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; WAVE32-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $scc
+ ; WAVE32-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY5]]
+ ; WAVE32-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY6]], implicit $exec
+ ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY5]], implicit-def $scc
+ ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
+ ; WAVE32-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY4]], 0, [[COPY3]], [[V_CMP_NE_U32_e64_]], implicit $exec
+ ; WAVE32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; WAVE32-NEXT: EXP_DONE 0, [[V_CNDMASK_B32_e64_]], [[V_CNDMASK_B32_e64_1]], [[COPY7]], [[COPY8]], -1, 0, 15, implicit $exec
+ ; WAVE32-NEXT: S_ENDPGM 0
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s32) = COPY $vgpr1
+ %3:vgpr(s32) = COPY $vgpr2
+ %4:vgpr(s32) = COPY $vgpr3
+ %5:sgpr(s32) = G_IMPLICIT_DEF
+ %6:sgpr(s32) = G_CONSTANT i32 2
+ %7:sgpr(s32) = G_ICMP intpred(eq), %0(s32), %6
+ %8:sgpr(s1) = G_TRUNC %7(s32)
+ %9:vcc(s1) = COPY %8(s1)
+ %10:vgpr(s32) = G_SELECT %9(s1), %1, %2
+ %11:vcc(s1) = COPY %8(s1)
+ %12:vgpr(s32) = G_SELECT %11(s1), %3, %4
+ %13:vgpr(s32) = COPY %5(s32)
+ %14:vgpr(s32) = COPY %5(s32)
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, %10(s32), %12(s32), %13(s32), %14(s32), -1, -1
+ S_ENDPGM 0
+...
+
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