[PATCH] D124014: [AArch64] Correct isLegalAddressingMode for ldp/stp

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Hmm. So I think that the current version of isLegalAddressingMode is technically correct - in that AArch64 does have r+r addressing modes for both scalars and vectors. (It might not for strange types, but that's not what we are targeting here). Adding a heuristic to make it wrong, so that the next level up produces better code is an option - but it may be better in the long run to fix the places using this (LSR for example) so that they understand about paired loads and can produce better code in all cases.

> And can you tell me if we do some perf sensitive change. what should we test ? I know some CPU perf bench like specCPU, cinebench, geekbench, but all of them are not open-source.

There are the benchmarks in the llvm-test-suite. They can be a bit noisy though, unfortunately, so need to be ran with care.


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