[llvm] 81af32b - [AMDGPU][MC][NFC][GFX940] Corrected an error position

[Dmitry Preobrazhensky via llvm-commits]

Author: Dmitry Preobrazhensky
Date: 2022-04-21T14:04:46+03:00
New Revision: 81af32b9a3ec0d0925f66ec972ce68c8d6f4ffe4

URL: https://github.com/llvm/llvm-project/commit/81af32b9a3ec0d0925f66ec972ce68c8d6f4ffe4
DIFF: https://github.com/llvm/llvm-project/commit/81af32b9a3ec0d0925f66ec972ce68c8d6f4ffe4.diff

LOG: [AMDGPU][MC][NFC][GFX940] Corrected an error position

Differential Revision: https://reviews.llvm.org/D124099

Added: 
    llvm/test/MC/AMDGPU/gfx940_err_pos.s

Modified: 
    llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 3987d11f622e1..c4590abbcb2d4 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4394,7 +4394,8 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
     if (CPol & CPol::GLC) {
       SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
       StringRef CStr(S.getPointer());
-      S = SMLoc::getFromPointer(&CStr.data()[CStr.find("glc")]);
+      S = SMLoc::getFromPointer(
+          &CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]);
       Error(S, isGFX940() ? "instruction must not use sc0"
                           : "instruction must not use glc");
       return false;

diff  --git a/llvm/test/MC/AMDGPU/gfx940_err_pos.s b/llvm/test/MC/AMDGPU/gfx940_err_pos.s
new file mode 100644
index 0000000000000..375350a668928
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx940_err_pos.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+
+//==============================================================================
+// instruction must not use sc0
+
+global_atomic_or v[0:1], v2, off sc1 nt sc0
+// CHECK: error: instruction must not use sc0
+// CHECK-NEXT:{{^}}global_atomic_or v[0:1], v2, off sc1 nt sc0
+// CHECK-NEXT:{{^}}                                        ^
+
+global_atomic_or v[0:1], v2, off sc0 sc1 nt
+// CHECK: error: instruction must not use sc0
+// CHECK-NEXT:{{^}}global_atomic_or v[0:1], v2, off sc0 sc1 nt
+// CHECK-NEXT:{{^}}                                 ^