[PATCH] D124148: [RISCV] Add special case to constant materialization to remove trailing zeros first.

[Craig Topper via Phabricator via llvm-commits]

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If there are fewer than 12 trailing zeros, we'll try to use an ADDI
at the end of the sequence. If we strip trailing zeros and end the
sequence with a SLLI we might find a shorter sequence.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124148

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
  llvm/test/CodeGen/RISCV/imm.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/MC/RISCV/rv64i-aliases-valid.s
  llvm/test/MC/RISCV/rv64zba-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

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