[PATCH] D123989: [RISCV] Add another test showing incorrect BUILD_VECTOR lowering

[Fraser Cormack via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG627e21048a2c: [RISCV] Add another test showing incorrect BUILD_VECTOR lowering (authored by frasercrmck).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123989/new/

https://reviews.llvm.org/D123989

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll


Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -745,3 +745,18 @@
 ; CHECK-NEXT:    ret
   ret <4 x i8> <i8 3, i8 3, i8 1, i8 0>
 }
+
+; FIXME: This is not a valid way to emit this vid sequence: shift-right for
+; division only works for non-negative numbers!
+define <16 x i8> @buildvec_not_vid_v16i8() {
+; CHECK-LABEL: buildvec_not_vid_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    li a0, -3
+; CHECK-NEXT:    vmul.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 3
+; CHECK-NEXT:    vadd.vi v8, v8, 5
+; CHECK-NEXT:    ret
+  ret <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 3, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0>
+}


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