[llvm] 186d5c8 - [RISCV] Make getInstSeqCost handle other Zb* instructions.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-04-20T22:08:04-07:00
New Revision: 186d5c8af5829bc4f6f0a3edcca43cef2d498c26

URL: https://github.com/llvm/llvm-project/commit/186d5c8af5829bc4f6f0a3edcca43cef2d498c26
DIFF: https://github.com/llvm/llvm-project/commit/186d5c8af5829bc4f6f0a3edcca43cef2d498c26.diff

LOG: [RISCV] Make getInstSeqCost handle other Zb* instructions.

We haven't been updating this as Zb* instructions have been used
for immediate materialization. They will hit the default case and
trigger an llvm_unreachable. Instead of trying to list them all,
assume instructions that aren't explicitly listed aren't compressible.

Spotted while looking at integer materialization for other reasons.
I haven't seen a crash from this yet.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 4adcd25600f20..0684aaabfdeec 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -18,10 +18,9 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
 
   int Cost = 0;
   for (auto Instr : Res) {
-    bool Compressed;
+    // Assume instructions that aren't listed aren't compressible.
+    bool Compressed = false;
     switch (Instr.Opc) {
-    default:
-      llvm_unreachable("Unexpected opcode");
     case RISCV::SLLI:
     case RISCV::SRLI:
       Compressed = true;
@@ -31,9 +30,6 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
     case RISCV::LUI:
       Compressed = isInt<6>(Instr.Imm);
       break;
-    case RISCV::ADD_UW:
-      Compressed = false;
-      break;
     }
     // Two RVC instructions take the same space as one RVI instruction, but
     // can take longer to execute than the single RVI instruction. Thus, we