[PATCH] D124096: [RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled.

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6893
+      if (N->getOpcode() == ISD::SHL && Subtarget.hasStdExtZbs() &&
+          isOneConstant(N->getOperand(0)))
+        break;
----------------
clang-format


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  https://reviews.llvm.org/D124096/new/

https://reviews.llvm.org/D124096