[PATCH] D124080: [RISCV] Support VP_ADD/VP_SUB/VP_MUL mask operation

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D124080#3462119 <https://reviews.llvm.org/D124080#3462119>, @frasercrmck wrote:

> I don't think this is the right way forward. This would be better handled in a target-independent way the same way `add/sub/mul` are handled, e.g, transformed to a canonical form. I believe this is during initial SelectionDAG creation though I haven't double-checked. So we'd expect `vp.add.v4i1` to be lowered to `ISD::VP_XOR`, etc. And since we already have mask-vector lowering for logical ops, RISCV shouldn't need any modifications.

I think it's buried inside of getNode.


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