[llvm] aa14e2e - [AMDGPU] Remove obsolete hack from allowsMisalignedMemoryAccesses. NFCI.

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2022-04-20T11:52:56-07:00
New Revision: aa14e2ef3e10abd36e422a5b8af116beac79e124

URL: https://github.com/llvm/llvm-project/commit/aa14e2ef3e10abd36e422a5b8af116beac79e124
DIFF: https://github.com/llvm/llvm-project/commit/aa14e2ef3e10abd36e422a5b8af116beac79e124.diff

LOG: [AMDGPU] Remove obsolete hack from allowsMisalignedMemoryAccesses. NFCI.

Differential Revision: https://reviews.llvm.org/D124035

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 27eda280089f1..246376aabaf71 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1658,18 +1658,6 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
 bool SITargetLowering::allowsMisalignedMemoryAccesses(
     EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
     bool *IsFast) const {
-  if (IsFast)
-    *IsFast = false;
-
-  // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
-  // which isn't a simple VT.
-  // Until MVT is extended to handle this, simply check for the size and
-  // rely on the condition below: allow accesses if the size is a multiple of 4.
-  if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
-                           VT.getStoreSize() > 16)) {
-    return false;
-  }
-
   bool Allow = allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
                                                   Alignment, Flags, IsFast);