[llvm] 5e54a41 - [LICM] Add additional writeonly tests, check attributes.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 20 10:49:44 PDT 2022
Author: Florian Hahn
Date: 2022-04-20T18:49:37+01:00
New Revision: 5e54a413de1f803718816dba35a59fbc4c7ed082
URL: https://github.com/llvm/llvm-project/commit/5e54a413de1f803718816dba35a59fbc4c7ed082
DIFF: https://github.com/llvm/llvm-project/commit/5e54a413de1f803718816dba35a59fbc4c7ed082.diff
LOG: [LICM] Add additional writeonly tests, check attributes.
Add additional test coverage for D123473.
Added:
Modified:
llvm/test/Transforms/LICM/scalar-promote.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LICM/scalar-promote.ll b/llvm/test/Transforms/LICM/scalar-promote.ll
index ad60bc87b910a..02fa9a5b3a151 100644
--- a/llvm/test/Transforms/LICM/scalar-promote.ll
+++ b/llvm/test/Transforms/LICM/scalar-promote.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes
; RUN: opt < %s -basic-aa -tbaa -licm -S | FileCheck %s
; RUN: opt -aa-pipeline=tbaa,basic-aa -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop-mssa(licm)' -S %s | FileCheck %s
target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
@@ -603,6 +603,7 @@ Out:
; Test case for PR51248.
define void @test_sink_store_only() writeonly {
+; CHECK: Function Attrs: writeonly
; CHECK-LABEL: @test_sink_store_only(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[GLB_PROMOTED:%.*]] = load i8, i8* @glb, align 1
@@ -639,7 +640,90 @@ exit:
ret void
}
+define void @test_sink_store_to_local_object_only_loop_must_execute() writeonly {
+; CHECK: Function Attrs: writeonly
+; CHECK-LABEL: @test_sink_store_to_local_object_only_loop_must_execute(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = alloca i8, align 1
+; CHECK-NEXT: [[A_PROMOTED:%.*]] = load i8, i8* [[A]], align 1
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[DIV1:%.*]] = phi i8 [ [[A_PROMOTED]], [[ENTRY:%.*]] ], [ [[DIV:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[LOOP_LATCH]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[I]], 4
+; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_LATCH]], label [[EXIT:%.*]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[DIV]] = sdiv i8 [[I]], 3
+; CHECK-NEXT: [[ADD]] = add i8 [[I]], 4
+; CHECK-NEXT: br label [[LOOP_HEADER]]
+; CHECK: exit:
+; CHECK-NEXT: [[DIV1_LCSSA:%.*]] = phi i8 [ [[DIV1]], [[LOOP_HEADER]] ]
+; CHECK-NEXT: store i8 [[DIV1_LCSSA]], i8* [[A]], align 1
+; CHECK-NEXT: ret void
+;
+entry:
+ %a = alloca i8
+ br label %loop.header
+
+loop.header:
+ %i = phi i8 [ 0, %entry ], [ %add, %loop.latch ]
+ %cmp = icmp ult i8 %i, 4
+ br i1 %cmp, label %loop.latch, label %exit
+
+loop.latch:
+ %div = sdiv i8 %i, 3
+ store i8 %div, i8* %a, align 1
+ %add = add i8 %i, 4
+ br label %loop.header
+
+exit:
+ ret void
+}
+
+; The store in the loop may not execute, so we need to introduce a load in the
+; pre-header. Make sure the writeonly attribute is dropped.
+define void @test_sink_store_to_local_object_only_loop_may_not_execute(i8 %n) writeonly {
+; CHECK: Function Attrs: writeonly
+; CHECK-LABEL: @test_sink_store_to_local_object_only_loop_may_not_execute(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = alloca i8, align 1
+; CHECK-NEXT: [[A_PROMOTED:%.*]] = load i8, i8* [[A]], align 1
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[DIV1:%.*]] = phi i8 [ [[A_PROMOTED]], [[ENTRY:%.*]] ], [ [[DIV:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[LOOP_LATCH]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[I]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_LATCH]], label [[EXIT:%.*]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[DIV]] = sdiv i8 [[I]], 3
+; CHECK-NEXT: [[ADD]] = add i8 [[I]], 4
+; CHECK-NEXT: br label [[LOOP_HEADER]]
+; CHECK: exit:
+; CHECK-NEXT: [[DIV1_LCSSA:%.*]] = phi i8 [ [[DIV1]], [[LOOP_HEADER]] ]
+; CHECK-NEXT: store i8 [[DIV1_LCSSA]], i8* [[A]], align 1
+; CHECK-NEXT: ret void
+;
+entry:
+ %a = alloca i8
+ br label %loop.header
+
+loop.header:
+ %i = phi i8 [ 0, %entry ], [ %add, %loop.latch ]
+ %cmp = icmp ult i8 %i, %n
+ br i1 %cmp, label %loop.latch, label %exit
+
+loop.latch:
+ %div = sdiv i8 %i, 3
+ store i8 %div, i8* %a, align 1
+ %add = add i8 %i, 4
+ br label %loop.header
+
+exit:
+ ret void
+}
+
define void @test_sink_store_only_no_phi_needed() writeonly {
+; CHECK: Function Attrs: writeonly
; CHECK-LABEL: @test_sink_store_only_no_phi_needed(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
@@ -669,6 +753,59 @@ exit:
ret void
}
+define void @sink_store_lcssa_phis(i32* %ptr, i1 %c) {
+; CHECK-LABEL: @sink_store_lcssa_phis(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]]
+; CHECK: loop.1.header:
+; CHECK-NEXT: br label [[LOOP_2_HEADER:%.*]]
+; CHECK: loop.2.header:
+; CHECK-NEXT: br i1 false, label [[LOOP_3_HEADER_PREHEADER:%.*]], label [[LOOP_1_LATCH:%.*]]
+; CHECK: loop.3.header.preheader:
+; CHECK-NEXT: [[PTR_PROMOTED:%.*]] = load i32, i32* [[PTR:%.*]], align 4
+; CHECK-NEXT: br label [[LOOP_3_HEADER:%.*]]
+; CHECK: loop.3.header:
+; CHECK-NEXT: [[I_11:%.*]] = phi i32 [ [[I_1:%.*]], [[LOOP_3_LATCH:%.*]] ], [ [[PTR_PROMOTED]], [[LOOP_3_HEADER_PREHEADER]] ]
+; CHECK-NEXT: [[I_1]] = phi i32 [ 1, [[LOOP_3_LATCH]] ], [ 0, [[LOOP_3_HEADER_PREHEADER]] ]
+; CHECK-NEXT: br i1 true, label [[LOOP_3_LATCH]], label [[LOOP_2_LATCH:%.*]]
+; CHECK: loop.3.latch:
+; CHECK-NEXT: br label [[LOOP_3_HEADER]]
+; CHECK: loop.2.latch:
+; CHECK-NEXT: [[I_11_LCSSA:%.*]] = phi i32 [ [[I_11]], [[LOOP_3_HEADER]] ]
+; CHECK-NEXT: store i32 [[I_11_LCSSA]], i32* [[PTR]], align 4
+; CHECK-NEXT: br label [[LOOP_2_HEADER]]
+; CHECK: loop.1.latch:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP_1_HEADER]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop.1.header
+
+loop.1.header:
+ br label %loop.2.header
+
+loop.2.header:
+ br i1 false, label %loop.3.header, label %loop.1.latch
+
+loop.3.header:
+ %i.1 = phi i32 [ 1, %loop.3.latch ], [ 0, %loop.2.header ]
+ br i1 true, label %loop.3.latch, label %loop.2.latch
+
+loop.3.latch:
+ store i32 %i.1, i32* %ptr, align 4
+ br label %loop.3.header
+
+loop.2.latch:
+ br label %loop.2.header
+
+loop.1.latch:
+ br i1 %c, label %loop.1.header, label %exit
+
+exit:
+ ret void
+}
+
!0 = !{!4, !4, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
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